SoC

June 20, 2017

Siemens sees Mentor helping to build fast digital twins

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
Article  |  Topics: Blog - EDA, Electrical Design, Embedded, PCB  |  Tags: , , , , , , , ,   |  Organizations: ,
June 20, 2017

ARM puts Cortex-M3 into DesignStart program

ARM has expanded its DesignStart program by providing access to the Cortex-M3 as well as the M0 with no up-front licence fee.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
June 19, 2017

Joe Costello claims IoT will drive wave of design

Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
March 21, 2017

ARM to re-spin Cortex for AI and servers

ARM has pulled together a number of forthcoming changes to its Cortex processor and Big-Little cluster architectures under the umbrella title DynamIQ, claiming they will support the increasing use of AI algorithms in servers and embedded control.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations:
November 9, 2016

Multicore standard works on fast communications

Work by the Multicore Association to provide a standard way for applications running on different processors to communicate with each other is leading to active implementations.
Article  |  Topics: Blog - Embedded  |  Tags: , , , , ,   |  Organizations:
October 13, 2016

ESD Alliance to describe system shift at DVCon Europe

Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
October 11, 2016

Achronix moves into embedded FPGA

Achronix has decided to offer the FPGA technology it has developed as a set of embeddable cores.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations:
December 11, 2015

IEDM keynote: cost scaling will swap architectural changes for area

According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations:
June 10, 2015

SoC verification ‘should use software more’

Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
May 18, 2015

Sonics readies fine-grained power-gating architecture

Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:

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