Mentor takes DFT planning to a higher level for hierarchical flows

By Chris Edwards |  No Comments  |  Posted: November 11, 2019
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations:

Mentor, a Siemens business, has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies as multicore SoCs become more prevalent and complex.

Geir Eide, product marketing manager for test at Mentor, said the divide-and-conquer approach to DFT implementation supported by hierarchical planning has helped deal with the capacity crunch that inevitably comes with the need for final test insertion to be performed in the final stages of chip implementation. By creating the DFT framework for each core individually before assembly, teams can save a lot of time but the integration process can involve many small changes that take time to perform and verify. Tessent Connect provides a methodology that is more intent-driven so that integration is easier to automate in the final stages.

Similar to the way that intent-driven design is used in PCB flows to instruct the placement and routing engines to make smarter decisions based on core design requirements, the intent-driven flow of Tessent Connect moves some test-insertion tasks to a higher level of abstraction with the information used in assembly inserted into a common database as each core is completed. As cores are brought together, the database provides the test-insertion tools with the information they need to ensure cores can be controlled and exercised by a test program.

Joseph Reynick, director of DFT services at eSilicon, an early adopter of Tessent Connect, said: “eSilicon uses Tessent Connect to help us meet our aggressive production schedules and deliver industry-leading ICs like those based on eSilicon’s neuASIC 7nm platform for machine learning. As design complexity continues to grow, our system/OEM customers’ needs expand from just focusing on high quality IC manufacturing test to also providing effective in-system test and functional debug capabilities. With today’s complex 2.5D/3D devices, we are not shipping in volume until our chips are fully operational in our customers’ systems, including DFT and IP test. It would be very difficult to meet these challenges without the Tessent DFT portfolio and the efficiencies gained from Tessent Connect automation.”

As part of the Tessent Connect rollout, Mentor today also announced the Tessent Connect Quickstart program, offering detailed flow assessments from Mentor’s applications and consulting services engineers.

“Our customers are continuously looking to reduce their test implementation costs as their design sizes grow and quality requirements become more stringent,” said Brady Benware, senior director of marketing for the Tessent product family at Mentor. “With Tessent Connect and the corresponding Quickstart program, our customers are empowered with an accelerated and automated path to DFT sign-off.”

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