October 8, 2020
As part of its move online during the pandemic, DVCon Europe is introducing what the organizers call Virtual Experience Rooms.
September 14, 2020
Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
August 27, 2020
Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.
August 25, 2020
TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
August 17, 2020
Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
July 31, 2020
Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
July 23, 2020
The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
July 21, 2020
Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.
July 21, 2020
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
July 21, 2020
Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.