DVCon to stick with virtual for Europe as US event highlights paper award

By Chris Edwards |  No Comments  |  Posted: March 18, 2021
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations: ,

DVCon to stick with virtual for Europe as US event highlights paper award

In the wake of the virtual DVCon wrapping up earlier this month, the organizers of the European iteration scheduled for the autumn have opted to go again with an online-only format, issuing a call for papers with a deadline of April 26.

According to Accellera, the virtual US-based event this month attracted more than 1300 attendees in a conference with a strong emphasis on improving the efficiency of verification. The winner of the Stuart Sutherland Best Paper Presentation, which is voted by conference attendees, focused on methods for making the most of formal verification in post-silicon bug hunting as well as in presilicon formal closure.

Described by Ping Yeung of Siemens EDA, the methodology the tools vendor has used with customers is based on a spiral refinement approach, where the spiral is a set of metrics displayed on a spider plot of capabilities. The idea is to gather information on the bug, set up a formal verification environment around it and then tune assertions and other factors to home in on the bug.

By collecting and reusing information, the process can be a lot faster than simply trying out lots of different approaches in a less targeted fashion. For example, for a bug in a memory controller, information on assertions that proved to work in one formal engine better than others was cached and reused to reduce overall runtimes. An important factor of the use of formal rather than simulation was that the team could focus better on actual root causes rather than a fix for a specific sequence of events that let other related bugs sneak past. In this particular customer’s case, it was possible to ship a firmware update that slightly reduced peak performance but which prevented the bug, which was triggered by an unusual set of circumstances, from resurfacing.

Yeung said the spiral technique has been used during formal closure, using the example of a packet scheduler. The big problem with verifying this kind of design is that large buffers make the verification runtime explode. So the spiral approach focused on reducing the checks to the core operation of the scheduler, gradually refining assertions and other parameters to reduce the number of channels, packet lengths and buffer sizes for outstanding transactions and so home in on core scheduler behavior.

Getting more from UVM

Second place for the Stuart Sutherland award was a paper presented by Cliff Cummings of Paradigm Works on a follow-up to a 2020 paper on reactive stimulus in UVM testbenches. The 2021 paper provided a way to give a testbench information on the DUT’s responses during verification and so react by providing more finely tuned stimuli. One issue with the previous approach was that the design of UVM made it hard to monitor outputs from interfaces that are not being probed directly. This new work adds an analysis FIFO that makes it possible to recover outputs from other parts of the DUT.

The third-place award was for a paper presented by Ioana Cătălina Cristea of Amiq, which looked at an open-source environment the company has built to improve the speed and visibility of assertions and their responses when those blocks need to be synthesized to run on a hardware emulator.

“I’d like to congratulate all of our paper and poster winners this year,” said Vanessa Cooper, DVCon US technical program committee chair. “Each presenter worked very hard to bring content to our attendees that would be valuable in their day-to-day jobs, helping them to be even more successful. We had a variety of presentations on topics ranging from RISC-V to UVM, to machine learning, and security and all were well-attended.”

The European event will take place on October 26 and 27, with a SystemC Evolution Day scheduled for October 28. The organizers says the aim of this year’s event is to strengthen collaboration with the functional safety and security community in order to support the development of necessary standards and methodologies.

The new General Chair of DVCon Europe is Sumit Jha. Sumit has been involved with DVCon Europe since 2019, acting as Poster Chair in 2020. The DVCon Europe 2021 Steering Committee is composed of technical experts from NXP, Intel, Bosch Sensortec, ARM, Infineon, Ericsson and Qualcomm.

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