Design-services company Sondrel is recommending teams start earlier on package design to avoid delays after IC tapeout.
The company said it has, through its turnkey programs for ASIC production, noticed increased lead times for SoC package design and manufacturing, particularly for flip-chip BGAs that can lead to delays in delivery.
“People think that they have to do things in a set sequence and hence don’t sort out the bump and ball co-ordinates until the design is finalized and ready to tape out to the fab,” said Ed Loverseed, Sondrel’s head of engineering. “Unfortunately, the increased lead times for packaging can now mean that the silicon will be produced before the packaging is ready.”
Once it became aware of this issue, Sondrel brought some parts of the package design forward using early floorplanning data to start to map out pad positions in the target package. The approach works by assigning die bumps and determining their x/y coordinates relative to the die corner well before top-level physical design and final RDL routing are completed.
Image Example bump map for an SoC
“Using the floor plan and the SoC partitions’ locations, the bump locations are determined for each of the macros and PHYs as specified by the IP vendors,” said, Alaa Alani, a principal engineering consultant and leader of the project. “For hard macros such as PCIe, HDMI and others, the bumps locations are specified by their relative offset from the macro corner whereas in soft macros, \[such as DDR memories], it is based on a certain pattern and a minimum pitch used in the bump assignment.
The final bump assignment still has to be checked against the final chip layout and there will be elements of the RDL and bump layout that will have to wait until later in the project. For example, general-purpose I/Os will be subject to changes until late in the design so the bump coordinates will inevitably be rough estimates until the the IC-level placement and routing are near completion. There may be some shifts in bump locations for soft macros during layout but, according to Sondrel, these changes will often be within IP guidelines and fab design rules.
The result is a speedup in overall delivery by doing more in parallel,. Alani notes, “We have found that this method gives an excellent first approximation that is good enough to start the SoC package planning and design. As a result, we have eliminated a potential delay and I would advise others to follow this procedure of starting bump layout early.”