Coherency verification for CXL

By TDF Staff |  No Comments  |  Posted: June 28, 2022
Topics/Categories: Blog - EDA, - HPC, Verification  |  Tags: , , , , , , , , , ,  | Organizations: , , , , , , ,

Maintaining cache coherency across heterogeneous systems is becoming more difficult as applications around AI and machine learning, high-performance computing and next generation communications exact greater demands.

Compute Express Link (CXL) is a powerfully-backed technology that “enables high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices” in the datacenter. Supporters include Alibaba, Cisco Systems, Facebook, Google, Huawei, Intel and Microsoft.

Verifying coherency in a CXL-fueled system faces the overarching problem of ensuring that the caches across multiple cores and their processors hold copies of the same high-risk data. A further challenge with CXL, however, is that it has many different options for requests, responses and combinations of cache state.

CXL is based on a PCIe Express 5.0 infrastructure to simplify implementation and the technology also takes a master-slave approach, with the CPU in charge. By comparison, another rival and broadly-supported connectivity technology, Cache Coherent Interconnect for Accelerators (CCIX), allows peer-to-peer connections (its supporters include AMD, Arm, IBM, Mellanox, Qualcomm, and Xilinx, as well as Huawei taking a dual role).

A new technical article from Siemens EDA, “Purging CXL Cache Coherency Dilemmas” sets out how to use verification IP – and the range of pre-defined stimuli, loggers, debug messengers and predictors within it – as part of a verification strategy built around four tenets.

  1. A verification plan with stimulus generation
  2. Cache checking
  3. Debug mechanisms
  4. Measuring coverage completeness

Based on the specific use of Questa VIP, it describes each of these steps in detail and their implementation for a heterogenous data centre project using CXL.

It argues that, VIP plays an important role because, “For verifying cache coherent systems verification plan
is essential but not sufficient. The complexity of creating and managing thousands of individual test cases is not feasible within realistic schedule constraints. There is a clear need for a wide range of pre-defined stimuli to ensure that you can achieve high coverage against your compliance goals.”

The article describing the proposed Questa VIP methodology for CXL is available for download here.


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