Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
EDA
Asymmetric variability issues could impact 7nm processes
Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
Cadence partners for photonic IC design
Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
Three key ways to reduce silicon test costs
Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
Ultrasoc tweaks debug technology to act as SoC burglar alarm
Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
Performance and timeout checks added to on-chip network
Sonics has add static performance analysis to its SonicsStudio tool and timeout detection to its SonicsGN network intended to prevent SoCs locking up.
Cadence shifts emulation to the data center
Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
DVCon Europe: UVM-SystemC backers ready first draft
But the bridge standard's European backers still need greater support from the big EDA vendors.
DVCon Europe: Getting TLM to cope with proliferating ECUs and serial protocols
High powered alliance develops TLM standards to address growing automotive and IoT concerns.
UltraSoC adds CoreSight and Ceva debug support
UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.