EDA

Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.

UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.

Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process

Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.

The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.

Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.

The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.

Following Mentor's acquisition of Tanner EDA, management expect the integration will help with a drive into IoT applications and systems that need to go beyond standard IC lithography.

Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.