EDA

HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.

Dassault Systèmes and IC Manage have each developed "big data" mining software tools to track the progress of chip-design projects

For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.

Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language

Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.

By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.

Silicon Cloud is preparing to expand access to its network-based design environment beyond the universities using it today to commercial users

Electronics design needs to cope with a combination of major brands and tiny start-ups looking to exploit its skills even where their resources are thin.

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes