network-on-chip


May 21, 2019

Achronix deploys network on chip for faster FPGAs

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Article  |  Topics: Blog - IP, PCB  |  Tags: , , , , , , , ,   |  Organizations:
February 18, 2019

UltraSoC scales up debug architecture

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
November 17, 2015

Performance and timeout checks added to on-chip network

Sonics has add static performance analysis to its SonicsStudio tool and timeout detection to its SonicsGN network intended to prevent SoCs locking up.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
November 11, 2015

UltraSoC adds CoreSight and Ceva debug support

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,
October 29, 2015

ARM targets cache-coherent GPU computing with CoreLink addition

ARM has developed a version of its CoreLink on-chip interconnect IP intended to support systems based on its big.Little processors combinations that need a cache-coherent GPU connection with lower latency and higher peak throughput.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations:
June 23, 2015

Sonics updates tune memory and link width for speed and power

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 9, 2014

Applications won’t find all the bugs, but they have their uses

Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
May 28, 2014

On-chip interconnect startup uses network theory to sidestep deadlocks

NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
August 2, 2013

Group plans better tools for multicore

A Japanese government-funded project has become the basis of a standard proposed by the Multicore Association that may provide a better way of supporting development for multicore systems.
Article  |  Topics: Blog - Embedded  |  Tags: ,   |  Organizations:
October 3, 2012

SAME: Memory-saving standard to expand

The scope of the Low-Latency Interface (LLI) developed by the MIPI Alliance is expanding as it heads towards version 2 – increasing the ways in which a single DRAM array can be shared between SoCs in a mobile phone.
Article  |  Topics: Commentary, Blog - EDA, - ESL/SystemC  |  Tags: , , , ,   |  Organizations: ,

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