network-on-chip

Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.

Sonics has add static performance analysis to its SonicsStudio tool and timeout detection to its SonicsGN network intended to prevent SoCs locking up.

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.

ARM has developed a version of its CoreLink on-chip interconnect IP intended to support systems based on its big.Little processors combinations that need a cache-coherent GPU connection with lower latency and higher peak throughput.

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.

Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.

NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.

A Japanese government-funded project has become the basis of a standard proposed by the Multicore Association that may provide a better way of supporting development for multicore systems.