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May 29, 2019

Synopsys introduces fast full-chip yield analysis and optimization tool

Synopsys has released PrimeYield, a tool for analysing and optimizing the yield of a design before it is made.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations:
April 10, 2013

ProPlus enters simulation with turbo-charged parallel SPICE

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
Article  |  Topics: Blog Topics, Design to Silicon, Verification  |  Tags: , , , , ,   |  Organizations:

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