EDA

Cadence has linked several machine-learning approaches to build a tool that is designed to speed up the detection and diagnosis of on-chip power-integrity issues.

Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.

Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.

Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.

From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.

Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.

MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.

Siemens and CEA-List have signed a deal under which the two organisations will research the combination of digital-twin and AI.

Get to know more on the specific benefits of shift left and how to achieve easy adoption.

Ultra Librarian has developed an AI-driven CAD modeling engine that should slash the the time it takes to build component and subsystem models for PCB layout and system design.