ITC 2023 preview: Siemens DIS

By TDF Editor |  No Comments  |  Posted: October 9, 2023
Topics/Categories: EDA - DFT  |  Tags:  | Organizations: , , ,

Siemens Digital Industries Software will be present across the program of the International Test Conference in Anaheim, CA this week from October 8 until October 13 in support of its Tessent platform.

Read on for more detail on its stand presence, technical papers, panel participation and Tessent tutorials.

However, a key announcement will extend Tessent’s ‘shift left’ capabilities for earlier insertion of more test logic at the RTL (more details here). The launch will be supported by a ‘Diamond Event’ in the Disney Grand Ballroom Center at 10:45 am on Tuesday October 10. Siemens’ company keynote presence will also include presentations on Smart DFT for Complex Semiconductor Design by Microsoft senior director Darshan Kobla and on How to Engineer a Smarter Future Faster by Ankur Gupta, vice president and general manager of Silicon Lifecycle Solutions at Siemens.

Disneyland Hotel

The Disneyland Hotel in Anaheim again hosts ITC 2023


The Siemens stand (Booth #2005) will have company and customer presentations on a range of topics, including:

  • Tessent Streaming Scan Network (SSN)  technology
  • SSN for In-system test
  • SSN on-the-fly optimization
  • Diagnosis with SSN
  • 3D IC solution – Tessent Multi-die
  • Tile-based design automation
  • ATPG Boost
  • Yield learning to boost manufacturing yields
  • Measuring analog test coverage

Technical papers

Within the ITC program itself, Siemens will be part of the xi on Wednesday afternoon (October 11, 12:00PM-2:00PM) and present papers during the following sessions:

Tuesday, October 10

A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy (presented by Oussama Laouamri at 1:30PM in Magic Kingdom Ballroom 1)

Global Control Signal Defect Diagnosis in Volume Production Environment (presented by Piotr Zimnowlodzki at 4:40PM in Magic Kingdom Ballroom 1)

Thursday, October 12

Predicting the Resolution of Scan Diagnosis (presented by Jakub Janicki by 11:00AM in Magic Kingdom Ballroom 2)

Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes (presented by Saidapet Ramesh of NXP with Siemens EDA at 1:30PM in Magic Kingdom Ballroom 1)


Janusz Rajski of Siemens DISW will join colleagues from Google, AMD, Intel, SMU and proteanTecs for a panel addressing Silent Data Corruption on Thursday (October 12) at 1:30PM in Magic Kingdom Ballroom 3.


Two Tessent workshops will round out the week on Friday (October 13).

The Role of Embedded Software in Realizing Silicon Lifecycle Management (hosted by Geir Eide, Rod Boyce, and Naga Nagarajan at 8:30AM)

Embedded Trace: A Key Enabler for Silicon Lifecycle Management (hosted by by Vivek Chickermane, Marcel Zak, and Mat O’Donnell at 1:00PM)

The International Test Conference takes place at the Disneyland Hotel in Anaheim with registration still available on site or online.

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