Verifying in an HLS context for AI and ML designs
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
Chipmaker
Building an ecosystem around HLS for AI and ML designs
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
The road to ES Design West: Systems
ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
RISC-V firms aim for lower-cost design starts
Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
The road to ES Design West: AI
AI, its system design implications and its impact on EDA tools themselves will be a key theme for ES Design West next month.
Calibre scales to 4000 nodes for faster sign off in the cloud
AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
The unknown unknowns of secure devices
Developing a security assurance standard for IP faces numerous problems but Accellera working-group members are trying to find an answer.
Cadence expands Protium for rack-based prototyping
Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
ARM adds Cortex-A77 and Mali-G77 cores for 5G and ML
The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
OneSpin extends line-up for AI FPGA and RISC-V verification
The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.