OneSpin extends line-up for AI FPGA and RISC-V verification

By TDF Editor |  No Comments  |  Posted: May 24, 2019
Topics/Categories: Blog - EDA, - Product, Verification  |  Tags: , , , , , ,  | Organizations: ,

OneSpin Solutions has extended its EC-FPGA automated sequential equivalence checking software to cover three of Intel’s field programmable gate array (FPGA) lines: Stratix 10, Arria 10 and Cyclone V.

The company has also launched an app for use inside its RISC-V Integrity Verification Solution aimed at safety- and security-critical applications and specifically targeting the increasingly popular open-source core.

OneSpin EC-FPGA for Intel

The Intel devices featured in the extension of EC-FPGA are used for applications in fields such as 5G, AI/ML, data center acceleration, high-performance computing and radar.

The use of complex, newly-minted IP across all of these fields as well as tightening power and timing specifications are making for extra challenges in ensuring the functional correctness of designs from the RTL stage to the final netlist.

EC-FPGA has been tailored for use with the Intel devices through vendor-supplied synthesis/place-and-route tool suites: Intel Quartus Prime Standard Edition for Cyclone V, and Intel Quartus Prime Pro Edition for Stratix 10 and Arria 10.

OneSpin says the tool is implemented in the FPGA flow from RTL to place-and-route to check RTL code against a post-synthesis, gate-level netlist.

RISC-V verification

RISC-V offers many options for configuration and micro-architecture as well as allowing designers to add custom extensions. Many users see these as advantages but they do complicate the process of ensuring compliance with the instruction set architecture (ISA).

OneSpin is therefore aiming to take an early lead in addressing this through its RISC-V Integrity Verification Solution.

Within that framwork, the company says that the new app, “identifies unspecified instructions and control and status registers, captures and verifies custom extensions allowed by RISC-V and formally verifies core compliance to the ISA, captured by a set of SystemVerilog Assertions. The app finds all compliance-related bugs. Once bugs are fixed, the app proves 100% compliance. Setup takes less than a week and requires two hours to run on a complete core.”

Both the RISC-V and FPGA product launches will feature within OneSpin’s presence at the Design Automation Conference next month.

 

 

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