A common theme for proponents of the RISC-V open-source instruction-set architecture is that it can be part of a movement to lower the barriers to entry of SoC design. Andes and SiFive have made moves to help make that a reality in the wake of the latest Design Automation Conference and the consortium’s workshop in Zurich.
Andes has launched what it calls the RISC-V FreeStart program: making the N22 processor, a compact low-power core, available for free download. SiFive has been rounding out its porfolio of cloud-based EDA tools for projects based around its RISC-V processor cores by signing up Avatar Integrated Systems, with the hope of adding more partners to the roster. “We would love to have all the different tool providers onboard,” says James Prior, SiFive’s senior director of product marketing communications. “It’s the start of a journey but not a completion. Avatar were the ones who were ready to move.”
UC Berkeley professor Dave Patterson claimed at the Design Automation Conference (DAC) last year that the goal for RISC-V “is very simple: it’s world domination”. The way he said this could be achieved would be through bringing some of the agile-development practices from the software world into chip design. “With agile hardware, everybody can do it and can afford it. It’s a great time to be in hardware again,” he claimed.
Patterson’s plan revolved around the use of cloud-based development platforms that include network-accessible FPGA systems for rapid prototyping. A second aspect of the plan is that it is oriented towards smaller microcontroller-like designs. “You can go a long way with small chips,” he argued.
“RISC-V is finding rapid adoption and creating high demand, especially in MCU-level applications,” claims Andes Technology president Frankwell Jyh-Ming Lin.
Cloud for development
Prior says the company’s promotion of cloud-based design is to “simplify the whole experience” and make it easier to refine and do fast iterations of SoCs that can then be taken to one of the company’s silicon partners. “We’re not trying to be a chipmaker,” he says.
Although Arm now has its own selection of cores with a low entry cost to support the design of products such as IoT-node controllers, Prior says the RISC-V model provides greater flexibility. “We are positioning in the sweet spot between FPGA and ASIC: for domain-specific or applications-specific processors. You can’t do that with Arm: for a lot of the modifications you might want you need an architectural licence.”
RISC-V offers the ability to add custom instructions to the pipeline as an alternative to coprocessors. However, Prior says the more common usage model is for SoC designers to make tweaks in the cache subsystem or to add tightly coupled peripherals.
With its RISC-V FreeStart program, Andes says teams can begin designing a RISC-V based SoC without budgeting for CPU IP upfront. Usage of the core in product designs will command royalty payments.
Andes CTO and executive vice president, Charlie Hong-Men Su, says: “The program also provides designers the option of one-year support and a pre-integrated AHB platform with commonly used peripheral IPs, thus saving the time of sourcing and integrating these into their design.”
The 32bit N22 core itself employs a two-stage pipeline and offers 16 or 32 general purpose registers, with multiplier, atomic and compressed instructions. It also supports configurable features that include hardware stack protection and power management.