CEVA splits vectors for more efficient 5G
CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
Chipmaker
Learn how Renesas uses SLEC to enhance its verification flows
A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
AI processor company opts for Analog FASTSPICE and Symphony
Mythic will use the Mentor tools for its analog-targeted intelligence processing units.
Arm adds AI to Cortex-M cores
Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
SureCore provides 30-day test for SRAM compiler
SureCore has started running 30-day trials of its low-power memory compiler.
Verific celebrates two decades of parser pre-eminence
The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.
MRAM pushes speed and endurance at IEDM
IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Siemens and Arm combine to extend digital twin further into SoC design
Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
On-demand DRC within P&R cuts closure time in half for MaxLinear
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm
Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
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