Cadence expands Protium for rack-based prototyping

By Chris Edwards |  No Comments  |  Posted: May 28, 2019
Topics/Categories: Blog - EDA, IP  |  Tags: , , , ,  | Organizations: ,

Cadence Design Systems has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.

Frank Schirrmeister, senior group director of product management in Cadence’s system and verification group, said: “This is an addition to the Protium family, not a replacement for the S1. We are re-segmenting the market into desktop prototyping and enterprise prototyping.”

With the X1, the target is the rack environment of the enterprise data center, with additional software support for multiple designs within a single unit and for multiuser access to the same design. The mapping software allows for situations where the internal cabling between the individual Xilinx UltraScale FPGAs that hold the designs is kept constant – to support fully remote usage – and for when to get better performance the links are moved around to match the partitioning. The front-end software for the X1 has also been designed to match that of the Palladium Z1 emulator to try to reduce bring-up times.

Although Cadence refers to the X1 processing units as blades, physically they resemble the removable-tray format that members of the Open Compute Platform have proposed for rack-based accelerators. Into these trays go the FPGA modules and connector arrays that form the hardware core of the Protium X1 platform. The trays are interconnected using cables that interface with the serdes ports of the FPGAs inside. Longer cables make it possible to link up to 256 modules across 32 racks to support the prototyping of billion-gate designs. Each tray can support up to 150 million emulated gates.

Partitioning help

Schirrmeister said the team has improved the mapping and partitioning process. One part of the tool indicates to users how best to deploy inter-module and inter-tray cables and connections. For example, the modules within the tray can use either direct connections from the standard FPGA I/O pins or multiplex signals through the serdes links. “The next step is to use machine learning to optimize these types of thing for partitioning,” Schirrmeister added.

Cadence plans further integration with the software from Green Hills, following the $150m investment announced in February in the Santa Barbara supplier of development tools and operating systems. The aim is to integrate support for the Multi debugger into the prototyping systems to help with software development. The second is to build flows that support safety- and security-oriented designs.

Schirrmeister said a key advantage of a platform such as Protium is the ability to inject simulated faults into the design. “They want to understand whether the system still works correctly within the context of failing hardware. It’s incredibly difficult to do this on a physical board. But we have a solution for it in Palladium and Protium: flip a bit and see if the software recovers appropriately.”

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