Codasip pips Arm to commercial CHERI with RISC-V version
Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
Archives
X-Fab adds galvanic isolation to CMOS process
X-Fab has made it possible to put galvanic isolation based on capacitive coupling directly into chips made on its XA035 process.
Companies partner for embeddable ReRAM
SureCore and Intrinsic have teamed up to provide a way to implement resistive random-access memory as an SoC-embeddable technology.
Imperas builds model of Tenstorrent AI core
Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.
Image sensors shrink at IEDM
This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
VLSI Symposium 2024 looks to bridge digital and physical
The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
Flow evolution for the 3DIC/chiplet age
Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
Accellera updates portable stimulus standard
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
ITC 2023 preview: Siemens DIS
From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.
Tessent speeds ‘shift left’ drive for test at RTL
Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.