DesignCon 2016 preview: Mentor Graphics

By TDF Staff |  No Comments  |  Posted: January 14, 2016
Topics/Categories: Conferences, Blog - PCB  |  Tags: , , , , , , , , , ,  | Organizations:

The team behind Mentor Graphics’ HyperLynx PCB analysis and verification software suite will be out in force at next week’s DesignCon 2016 (January 19-21). This year’s conference takes place at the Santa Clara Convention Center.

On the stand during exhibition days (January 20 and 21, 12:30pm-6.00pm), Mentor will be running demos featuring capabilities and the latest HyperLynx innovations in SERDES channel optimization, power integrity analysis, electrical rule checking and 3D electro-magnetic extraction.

“Digital designers must learn new methodologies like channel operating margins (COM), pulse amplitude modulation with four states (PAM4), and hybrid memory cube (HMC) and other 3D memory architectures,” notes Mentor’s preview.

“To accurately model advanced signaling protocols, they must combine 2D and 3D approaches with s-parameters, IBIS-AMI, and other models to create an accurate representation.

“They must create an electrical sign-off process that encompasses efficient constraint definition at the beginning, adherence to the constraints during layout, and full-board validation at the end.”

Expect these and other issues to also be addressed in an Advanced Modeling and Analysis seminar Mentor is offering at DesignCon 2016 on Thursday (full details below).

HyperLynx will also feature in a Wednesday (January 20) DesignCon 2016 technical session, BER- and COM-way channel compliance evaluation: What are the sources of difference? (2.50-3.30pm, Ballroom A, SCCC).

HyperLynx seminar at DesignCon 2016

The full program for the Advanced Modeling and Analysis Seminar (Great America 3, SCCC, January 21)

  • 8:30am – 9:10am: Deciphering mainstream SERDES design analysis for signal integrity and hardware design engineers
  • 9:20am – 10:00am: Incorporating COM into an signal integrity analysis methodology
  • 10:15am – 10:55am: DDR4: New design challenges
  • 11:05am – 11:45am: Efficiently screening miniscule to massive boards for signal integrity, power integrity, and electromagnetic interference issues
  • 2:00pm – 2:40pm: Automated channel extraction for 25Gb/s links
  • 2:50pm – 3:30pm: A holistic approach to IC, package and board co-optimization


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