DesignCon 2017 preview: Mentor Graphics

By TDF Staff |  No Comments  |  Posted: January 17, 2017
Topics/Categories: Conferences, Blog - PCB  |  Tags: , , , , , , , , ,  | Organizations: , ,

PCB-led conference DesignCon 2017 will be held at the Santa Clara Convention Center from Tuesday, January 31 to Thursday, February 2 (Exhibition Feb 1 and 2 only). Mentor Graphics’ presence will concentrate on tools within the HyperLynx family and also include a number of dedicated technical sessions.

On stand #1043, the HyperLynx elements will focus on power and signal integrity solutions, as well as design rule checks for issues related to those challenges and electromigration, and the use of a full-wave electromagnetic solver.

The booth will also feature the Frontline InStack Design tool: this automates stack-up selection according to project criteria based on quality, manufacturability and price.

DesignCon 2017 will take place at the Santa Clara Convention Center

DesignCon 2017 will take place at the Santa Clara Convention Center

DesignCon 2017 technical sessions

At time of writing, registration is still open for three Mentor technical events during DesignCon 2017 (click on any of the session titles for their registration pages). These are:

Optimization methods for high speed SERDES channels using COM metric

Wednesday, February 1, 11:00am – 11:45am, Ballroom G

Attendees will learn about the use of the Channel Operating Margin (COM) as a criterion for validation as well as optimization, and the session will also review the advantages and disadvantages of  analysis and optimization based on methods such as DOE, RSM, and evolutionary computation.

Channel Operating Margin (COM) for PAM4 links with support fro TX non-linearity and time skew

Thursday, February 2,11:00am – 11:45am,  Ballroom D

This session, a joint presentation by Mentor and Tektronix, will consider ways of refining COM as a link margin tool to account for benefits that PAM4 links can derive from non-linearities. In its standard form, COM considers non-linearities to be penalties. This session does assume some familiarity with both PAM2 and PAM4 modulation as well as the general implementation challenges associated with them.

SI analysis of DDR bus during read/write operation transitions

Thursday, February 2, 4:00pm – 4:45pm, Ballroom C

At the higher speeds now offered by (LP) DDR4, traditional simulation techniques are coming under strain as times between operations shorten. Such transition times were until now given less priority during simulation, yet have an increasing impact on signal integrity. This session will show attendees when and how to perform simulations to model these transitions effectively.

Best paper – DesignCon 2016

Mentor has also posted the winner of best paper at DesignCon 2016 for download free-of-charge (registration required).

BER and COM channel compliance’ analyzes the computational procedure specified for Channel Operation Margin (COM) and compares it to traditional statistical eye/BER analysis.

As well as English, the paper is available in Mandarin (Simplified), Korean and German.

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