SureCore provides 30-day test for SRAM compiler

By Chris Edwards |  No Comments  |  Posted: January 24, 2020
Topics/Categories: Blog - IP  |  Tags: , , , ,  | Organizations:

SureCore has started running 30-day trials of its low-power memory compiler for potential users to evaluate the capabilities of its PowerMiser and EverOn standard SRAM IP.

The Compiler Access Program (CAP) is available to SoC designers to test the performance and low power capabilities of SureCore’s low power SRAM on 22nm, 28nm or 40nm bulk and SOI processes.

“AI, imaging, IoT, medical, and wearable devices all require enhanced power profiles. With SRAM integration levels continuing to rise, our standard products help deliver the power savings needed in these competitive market spaces. Through CAP, we’re opening a low power memory test drive to optimize power budgets and manufacturability,” said Paul Wells, sureCore’s CEO.

As well as building SRAM macros the CAP will generate datasheets that cover detailed PPA information, including access times, dynamic power, and sleep/deep sleep/standby leakage power, based on the requested instances and operating environment. Companies can apply for access to CAP at www.sure-core.com.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors