functional verification

February 22, 2016

DVCon United States 2016 preview: Real Intent

Verification specialist's DVCon activities are headlined by a panel on emulation and static verification.
February 22, 2016

DVCon United States 2016 preview: Mentor Graphics

Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.
November 16, 2015

Cadence shifts emulation to the data center

Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
June 10, 2015

SoC verification ‘should use software more’

Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
May 21, 2015

OneSpin uses app-store approach to open up formal verification

Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.
April 28, 2015

Cadence upgrades debug for system-level era

Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
April 22, 2015

Thursday returns as DAC training day

The Design Automation Conference in San Francisco this year will again feature a day of half-day training courses provided by Doulos on Thursday, June 11 .
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
February 11, 2015

Accellera sets up group for one-stop verification stimulus

Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
December 11, 2014

Use-cases drive high-level verification tool

Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.
Article  |  Topics: Product, RTL, Verification  |  Tags: , , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors