Verilog


February 18, 2019

How to optimize your testbench-to-DUT connections

Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
February 25, 2015

Real Intent updates linter for aviation, Mathworks and SystemVerilog

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.
Article  |  Topics: Product, RTL, Verification  |  Tags: , , , , ,   |  Organizations:

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