Verilog

July 1, 2020

Sigasi creates SDK for custom editors

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.

Article | Topics: Blog - EDA | Tags: custom tools, editor, HDL, IDE, SystemVerilog, Verilog, VHDL | Organizations: Sigasi, Xilinx

February 18, 2019

How to optimize your testbench-to-DUT connections

Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.

Article | Topics: Blog - EDA, - Tested Component to System, Verification | Tags: abstract classes, DUT, interface, SystemVerilog, testbench, Verilog, virtual interface, whiteboxing | Organizations: DVCon, Siemens EDA

February 25, 2015

Real Intent updates linter for aviation, Mathworks and SystemVerilog

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.

Article | Topics: Blog Topics, Standards, Verification | Tags: aviation, avionics, DO-254, high level synthesis (HLS), lint, SystemVerilog, Verilog, VHDL | Organizations: MathWorks, RealIntent

July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.

Article | Topics: Product, RTL, Verification | Tags: functional verification, static verification, SystemVerilog, Verilog, VHDL, x propagation | Organizations: RealIntent

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