Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.
Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.
In Las Vegas, the parser specialist will demonstrate its tools for EDA software development across VHDL, SystemVerilog and UPF.
Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
More than 20 new features and improvements are added to the static functional tool.
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL