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May 25, 2016

Register tools appear ahead of DAC

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
May 21, 2015

OneSpin uses app-store approach to open up formal verification

Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.
May 21, 2015

Agnisys automates register checks

Agnisys is adding automated verification of SoC register maps to its IDesignSpec tool for defining and specifying registers and their behaviours, deploying both a dynamic and a formal version.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
July 30, 2013

Three Accellera proposals aim for better TLM

Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,

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