Real Intent’s latest release of its Ascent Implied Intent Verification (IIV) suite adds a range of debug features aimed at pushing the capabilities of static functional verification beyond what traditional Verilog or VHDL can offer. The updated software is available for immediate download from the company’s website.
Ascent IIV is an automatic RTL verification tool that uncovers bugs using an intelligent hierarchical analysis of design intent. No test bench or assertions are required, with the goal that this will make it easier and more efficient to find RTL bugs earlier in the design flow.
Specific enhancements and new features in this Ascent IIV release include:
- Specialized report categories for FSMs, language checks, design checks, coverage, and X-verification with control of report depth for easier debug review
- Causality reporting, which shows the secondary errors caused by each primary error so designers can rank the impact of fixing primary errors
- New language checks for violations of SystemVerilog constructs – unique, priority, and enumeration
- Easier setup for quick adoption
A further 15 new analysis and debug improvements have also been made to Ascent IIV.
Lisa Piper, senior manager of technical marketing at Real Intent, said, “Our new specialized reports make it easier for designers to focus on categories of concern, tailor the results, and see the impact of fixing primary errors.
“For the first time, IIV now has checks for SystemVerilog constructs that are not in classic Verilog code..”
Piper discusses the release further and highlights trends in automatic verification in a YouTube interview posted today.