The numbers point to established and continuing growth in semiconductors but EDA will need to innovate around three types of scaling to ensure the industry delivers on current promise.
That was a key message in the recent DAC keynote from Joe Sawicki, Executive Vice President for IC EDA at Siemens.
Sawicki cited a series of data for current performance alongside projections that support a renewed “optimism and swagger” across the sector and illustrate the benefits it is already drawing from “digitalization”.
For example, after the double hit of the dot-com bubble followed a few years later by a major recession, the chip market had suffered slower growth than global GDP but is now moving ahead again at 9.2 per cent CAGR against 6.2 per cent (Figure 1).
Behind that, artificial intelligence is an area that is drawing together design across four key enablement areas: sensors, edge computing, 5G and wireless, and cloud and datacenter.
Sawicki noted the increasing chip content going into automobiles: an average of $499 per car last year and 997 devices against $307 for 624 devices in 2010. Content and value are on track to increase yet further to $758 and 1,277 devices by 2030.
He also showed that big system companies are placing ever greater emphasis on silicon, often bringing design in-house. They now account for 21.3 per cent of foundry wafers from barely any a few years ago.
And amid all this activity, EDA is already seeing benefits. according to data compiled by the ESD Alliance. In its most recent release of market statistics, Q2 2021 revenues reached $3.2bn across all vendors, up 15.5 per cent year-on-year and marking the fourth consecutive quarter of double-digit growth.
“I don’t know that we’ve had a time in the last 20 years when we could be as optimistic about what’s going to be happening in terms of semiconductors,” Sawicki said. “Lots of trends are going to be driving growth, lots of trends where we become more and more important in terms of end customers and what these industries are delivering to their customers, And that’s driving a new level of activity in terms of design, and it’s driving new revenue for the EDA industry.”
But there are things that need to be addressed. Sawicki bracketed these mainly in three areas: Technology Scaling, Design Scaling and System Scaling.
Technology Scaling is needed to continue to reach the main targets within Moore’s Law, even if classical scaling is a thing of the past. It will involve continued innovation by EDA and the industry as a whole around not just the traditional ‘monolith’ but also in fields such as advanced packaging and concepts such as chiplets.
“These are not easy nodes – and I don’t even know what we’re going to call them once we get beyond 1nm,” Sawicki said. But, he believes that the vast amounts of data generated around device and package manufacturing today will lend itself well to the use of machine learning and pattern analytics for DFM and other design challenges.
For Design Scaling, the battle is largely set toward controlling some of the more pessimistic forecasts for NRE costs. Here Sawicki said Siemens would continue to bang the drum for high-level synthesis as delivering productivity gains through abstraction, and is also going to push hard on the emerging space for System Technology Co-Optimization.
Then in System Scaling, a key factor in Siemens’ acquisition of the original Mentor EDA business, Sawicki sees an expansion of the verification and validation process allowing designs not only to be verified in and of themselves, but also within their application spaces and in digital twin environments that offer real world simulations of ever greater fidelity.
He also sees EDA specifically needing to offer more towards silicon lifecycle issues such as in-built self-test for functional safety, in-the-field performance monitoring, and features and tools that address reliability and aging.
“We have, Sawicki concluded, “a very rich set of problems ahead of us, that will allow us to continue to innovate, and move forward into the future.”