AXI


April 28, 2015

Cadence upgrades debug for system-level era

Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
May 28, 2014

On-chip interconnect startup uses network theory to sidestep deadlocks

NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:

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