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December 11, 2014
Use-cases drive high-level verification tool
Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
Article | Topics:
Blog - EDA
,
Embedded
,
IP
| Tags:
functional verification
,
software-driven verification
,
UML
,
use-case
,
verification coverage
| Organizations:
Cadence Design Systems
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