GlobalFoundries licenses atomistic TCAD simulator toolchain
Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
FD-SOI
OpenPDK accelerates design kit production at ST
STMicroelectronics is using the OpenPDK standard from Si2 to speed up the production and delivery of process design kits (PDKs) and asks for wider adoption by foundries.
14nm FD-SOI pushes strain and body bias for power savings
At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Cadence ports IP and qualifies tools for 28nm FD-SOI
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Samsung agrees to make 28nm FD-SOI
STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.
Qualcomm’s take on preserving Moore’s Law economics
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
Design kit for 10nm FD-SOI due out next year
Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
CMOS “good for another century,” says father of finFET
CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
SureCore picks up grant for low-power, nanometer SRAM IP
Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.
Intel and ST stake claims to foundry low power designs
With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.
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