FD-SOI

May 17, 2014

Cadence ports IP and qualifies tools for 28nm FD-SOI

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
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May 14, 2014

Samsung agrees to make 28nm FD-SOI

STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.
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December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
October 4, 2013

Design kit for 10nm FD-SOI due out next year

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
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June 3, 2013

CMOS “good for another century,” says father of finFET

CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
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May 15, 2013

SureCore picks up grant for low-power, nanometer SRAM IP

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.
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March 27, 2013

Intel and ST stake claims to foundry low power designs

With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.
March 19, 2013

FD-SOI costs to match bulk by year end, says ST

STMicroelectronics pushes on with FDSOI despite dissolution of ST-Ericcson joint venture that provided the lead customer for the process.
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February 5, 2013

GlobalFoundries and Samsung talk finFET progress at CPTF

GlobalFoundries and Samsung described how they are readying finFETs for production at CPTF 2013 and how the 28nm processes will have a long shelf life.
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December 11, 2012

FD-SOI vs finFETs mulled during IEDM

Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs

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