The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.
CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
The EDA industry has a way to capture the embedded software market, analyst Gary Smith said ahead of DAC. But it’s not through tools – it’s through models.
A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.
DAC 2013's technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.
Whether your going to DAC 2013 or not, the EDA analyst's round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.
Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
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