FD-SOI

May 11, 2017

Racyics puts FD-SOI design flow online

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.
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September 16, 2016

GlobalFoundries ports MRAM to 22nm FD-SOI

GlobalFoundries has introduced an embedded-MRAM option for its 22nm FD-SOI process: the 22FDX platform.
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April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
July 13, 2015

GlobalFoundries tunes 28nm for smaller, lower-power FD-SOI

GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.
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June 8, 2015

CEA-Leti adds partners to FD-SOI low-power design centre

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
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May 25, 2015

Shape a major choice for sub-10nm nanowire FETs

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
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March 12, 2015

Cea-Leti opens FD-SOI design center

CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.
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March 11, 2015

IoT and RF ‘to drive FD-SOI adoption’

The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , ,
March 11, 2015

Charting out the roadmap for FD-SOI

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
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January 7, 2015

CEA-Leti deals with heat issue on monolithic 3DIC

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
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