September 16, 2016
GlobalFoundries has introduced an embedded-MRAM option for its 22nm FD-SOI process: the 22FDX platform.
April 7, 2016
But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
July 13, 2015
GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.
June 8, 2015
Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
May 25, 2015
TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
March 12, 2015
CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.
March 11, 2015
The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
March 11, 2015
As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
January 7, 2015
At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
July 25, 2014
Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.