Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
Mears Technologies and UC Berkeley describe at IEDM 2012 how oxygen in a silicon superlattice could boost performance beyond strained silicon at 14nm.
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.
What are the chances that FD SOI will become a mainstream process for future nodes?
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