Cadence ports IP and qualifies tools for 28nm FD-SOI

By Chris Edwards |  No Comments  |  Posted: May 17, 2014
Topics/Categories: Blog - EDA, IP  |  Tags: , , , ,  | Organizations: , ,

Cadence Design Systems has developed two sets of intellectual property (IP) aimed at the 28nm FD-SOI process developed by STMicroelectronics.

On this process node, Cadence said its Denali DDR4 memory interface IP supports up to 2667Mbit/s performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to take advantage of the DDR4 standard. In addition, a low-power USB High-Speed Inter-Chip (HSIC) PHY IP has also been made available on this process.

The Cadence Denali DDR4 IP offering consists of a DDR PHY and controller that have been verified in silicon for interoperability and offer features such as per-bit de-skew capability, low-jitter phase-locked loops (PLLs) and compatibility with DDR3 and DFI 3.1.

The Cadence HSIC PHY IP is a mixed-signal transceiver macro-cell that implements the USB 2.0 HSIC layer for USB 2.0 high-speed device and host applications. Cadence says coupling the HSIC PHY interface with the STMicroelectronics HSIC PHY I/O provides very low power consumption and silicon area.

Cadence has also said it has qualified its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process, including Encounter, QRC for extraction, Tempus, Spectre, Virtuoso Analog Design Environment, and Virtuoso Layout Suite.

Martin Lund, Cadence’s senior vice president and general manager of the IP group, said: “From early on, Cadence has worked with STMicroelectronics on FD-SOI technology and can assure our customers that they can quickly implement these IP solutions and sign off their designs.”

“FD-SOI technology delivers superior energy efficiency at the 28nm node and allows for a wider range of dynamic voltage and frequency scaling, leading to higher processing power per watt, lower thermal dissipation, and extended battery life for portable devices,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics. “Having just announced a leading foundry partner and now adding prominent IP and EDA suppliers like Cadence expands the growing ecosystem, for the benefit of our mutual customers and the entire electronics industry.”

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors