SureCore picks up grant for low-power, nanometer SRAM IP

By Chris Edwards |  1 Comment  |  Posted: May 15, 2013
Topics/Categories: Blog - EDA, IP  |  Tags: , , , ,  | Organizations:

UK-based physical-IP startup SureCore has been awarded £250,000 ($380,000) to perform R&D on a low-power SRAM design that the company is putting together for future process nodes.

The UK’s Technology Strategy Board has decided to give SureCore one of its SMART awards for the development of a demonstrator chip that will be used to test the company’s array control and sensing scheme. The company claims its approach will lower active power consumption and is working with foundries on FD-SOI (Guide)  and finFET (Guide) implementations.

The company has used statistical modelling – one of its directors is leading variability and statistical modelling researcher Professor Asen Asenov – to develop the SRAM IP and come up with a way of lowering power consumption, which SureCore claims will be less than half that of existing approaches.

Paul Wells, CEO of SureCore, said: “We have proven the technology in simulation but to fully characterise and demonstrate its benefits implementation in silicon is a must. This is a critical next step in demonstrating the value of our IP to our customers.”

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