Even EUV faces a 1D future, says IMEC

By Chris Edwards |  No Comments  |  Posted: March 26, 2014
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations:

Don’t like the idea of 1D design? The industry might have to get used to it the way that Intel’s processor designers have in order to enjoy further steps down the scaling ladder.

In a panel on the challenges facing the semiconductor industry at DATE in Dresden, Rudy Lauwereins, vice president of research institute IMEC explained how 1D routing is likely to be inevitable even if EUV makes it into production fabs.

Lauwereins pointed to the current manufacturability issues that faces users of litho-etch, litho-etch (LELE) double patterning in which two complementary photomasks need to be exposed in sequence. To guarantee that contacts match up within the overlay tolerance, fabs have had to work with more relaxed pitches than designers would like. Rather than a pitch of 40nm for interconnect lines on a process built for the 10nm generation, or N10 in IMEC’s terminology, the realistic metal-one pitch using LELE is more like 48nm.

To overcome the overlay problem, fabs could switch to self-aligned double patterning (SADP) or, to use Intel’s terminology, pitch splitting. The consequences of this can be seen in teardowns of Intel’s recent processors – lower-level interconnect masks that look like diffraction gratings. Companies such as nVidia have been working on the basis that they may need to switch to 1D techniques for the 10nm generation.

“You need to go to L-shaped patterns or even 1D interconnect using self-aligned double patterning, which moves the problem to the EDA side,” said Lauwereins. “Using this system it is possible to get to a 40nm pitch. But if we go to EUV later, we wouldn’t need 1D for the next generation – N7. The question is: does EDA invest for 1D for one process generation?”

Lauwereins said there remains a risk that EUV will not even be ready for N7, which implies the use of self-aligned quadruple patterning for that node. Intel’s director of lithography indicated several years ago at the VLSI Technology Symposium that the processor maker would be able to work on that basis. So, at least one company is working on the basis that 1D routing is here to stay. But, even if EUV is ready, 1D is likely to be the future, said Lauwereins.

“By N5, even EUV will need self-aligned double patterning. We need 1D routing for EUV anyway eventually. So, it’s a safe bet for EDA to work on this 1D routing technology,” Lauwereins claimed.

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