7nm finFET process techniques lead IEDM lineup

By Chris Edwards |  No Comments  |  Posted: October 24, 2016
Topics/Categories: Blog - EDA  |  Tags: , , , , ,  | Organizations:

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.

Foundry TSMC and a technology development alliance of IBM, Globalfoundries and Samsung have submitted late-news papers to describe what they have done to make 7nm finFETs viable at their respective fabs in anticipation of process introductions during 2018.

TSMC aims to describe how it is tuning its 7nm finFET process for mobility applications. According to TSMC, the proposed technology features more than three times the gate density and either a speed gain (35-40 per cent) or power reduction (>65 per cent) versus the company’s commercial 16nm FinFET process.

To demonstrate the technology, TSMC’s researchers built a fully functional, low-voltage 256Mbit SRAM test chip with full read/write functionality down to 0.5V, and the smallest SRAM cells ever reported (0.027µm2). The process is manufacturable using 193nm immersion lithography and employs an epitaxially raised source and drain design that strains the transistor channel for greater carrier mobility as well as a contact structure designed to reduce resistance.

The 7nm FinFET technology to be disclosed by the IBM/Globalfoundries/Samsung technology development alliance has been designed around the use of extreme ultraviolet (EUV) lithography to pattern transistors. According to the alliance, EUV lithography and other advanced patterning approaches have led to the tightest contacted polysilicon pitch (44/48nm) and metallization pitch (36nm) ever reported for FinFETs. The technology also features dual-strained channels on a thick strain-relaxed buffer virtual substrate to combine tensile-strained NMOS and compressively strained SiGe PMOS for enhancement of drive current by 11 per cent and 20 per cent, respectively, versus a common planar HKMG process. It also features novel trench epitaxy to minimize the resistance of the highly scaled contact regions.

Focus sessions

To be held at the Hilton San Francisco Union Square Hotel from December 3 – 7, 2016, the conference will also feature four special-focus sessions with invited papers from world experts describing the latest research in: wearable electronics and the internet of things; quantum computing; wide-bandgap high-power devices; and terahertz electronics.

Among the submitted papers that look at high-energy devices is work by Panasonic that attempts to improve the power handling of gallium nitride (GaN) through the use of near-vertical structures. Planar AlGaN/GaN transistors on silicon substrates are commercially available with blocking voltages of up to 600V but vertical structures that can improve blocking voltages and efficiency are not feasible. Panasonic researchers used a V-shaped structure for their devices built on a bulk GaN substrate (p-GaN/AlGaN/GaN) with a record-setting 1.7kV threshold voltage plus a remarkably low on-state resistance of 1.0 mΩcm2. Because these grooves for the drift layer were cut at a slant, they exposed a second facet of the crystalline GaN material and thereby created the possibility of semipolar operation.

10nm developments

This year sees the return of the idea of using air spacers to reduce parasitic capacitance in interconnect, in this case aiming at the tightly packed gate and contact structures around the finFET rather than upper layer metal wires. Researchers from IBM and Globalfoundries will report the first air spacers at the 10nm FinFET node. These reduced capacitance at the transistor level by as much as 25 per cent, and in a ring oscillator test circuit by as much as 15 per cent. The researchers say a partial air spacer scheme represents a good way to introduce air spacers at this scale because it minimizes damage to the FinFET, as does the high-selectivity etching process used to fabricate them.

Also looking at the 10nm node, Samsung researchers will present the first comprehensive reliability analysis of the FinFET technology. They will review all major aspects of multiple-threshold-voltage FinFET technology including hot carrier injection, intrinsic ballistic transport, and gate and middle-of-the line time-dependent dielectric breakdown (TDDB). They will describe process optimizations that overcome roadblocks to FinFET device technology at this node, such as self-heating effects, and will describe robust 10nm devices they built that demonstrated high reliability.

In terms of novel devices, researchers from Stanford University will describe brain-like processing using 3D vertical resistive memories (RRAMs). The approach the team has taken differs from traditional neural-network learning in that the self-learning process involves very little training data. The idea behind the use of RRAM is to allow the storage of intermediate values between zero and one. The team claims the computing framework was able to recognize words in 21 different languages from a variety of sample texts.

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