SADP

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.

IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.