Path to 5nm plotted at DAC panel

By Luke Collins |  No Comments  |  Posted: June 13, 2014
Topics/Categories: Conferences, Blog - EDA  |  Tags: , , , , , ,  | Organizations: , , ,

How will we get to 5nm processes, and will it be worthwhile to do so? A panel at last week’s Design Automation Conference considered the issue from the perspective of an IDM, foundry, equipment supplier and fabless company.


Asked about the biggest challenge that the industry faced to go beyond 14nm processes, Lars Liebmann, distinguished engineer at IBM’s Semiconductor R&D center, and technical lead for its 14nm, 10nm and 7nm processes, said: “The biggest challenge is there is no one challenge.”

He argued that for a long time, the industry had been driven by dimensional scaling, enabled by improvements in lithography at decreasing wavelengths and increasing numerical apertures.

As of now, reducing feature sizes increases leakage and so undermines performance gains. Moving to advanced multipatterning approaches, such as eight-way patterning, will not be cost effective, so the industry must find other ways to progress.

“You can solve any one problem at a time, but something else pops out.”

Adam Brand, senior director of the transistor technology group at Applied Materials, said he thought there were three major problems: patterning below the 20nm pitch “which is likely to take quadruple patterning and cut masks’; how to make the device work; and how to keep scaling the operating voltage of the transistor.

“The ability to continue reducing the voltage is without solution at the moment,” he said.

Srinivas Banna, a fellow at GlobalFoundries, gave the manufacturer’s view: “We need multiple innovations per node, therefore scheduling the R&D to deliver that becomes more difficult.”

He argued that beyond the 14nm and 10nm nodes, the industry may need to go to a different substrate, which will drive cost.

Karim Arabi, vice president of engineering at Qualcomm highlighted the accelerating pace of change In the industry: “We have never moved to new technologies faster than today: Moore’s Law is not stalling, it’s going faster. The problem is the economy of Moore’s Law: economic scaling is not getting cheaper.”

How will these problems get solved? One clear consensus on the panel was the need for early collaboration with tools vendors.

“Early engagement is the only way to meet your goals,” said Banna, pointing out that innovations such as the need to colour designs to meet double-patterning requirements was already changing the way is done.

Moore’s Law no more?

Asked if and when Moore’s Law would stop mattering stopped mattering, Arabi at Qualcomm said that “Moore’s Law is a self-fulfilling prophecy that we all rallied around and it became a benchmark around which to compete.”

As it becomes more difficult to rely on pure scaling to deliver power/performance/area improvements, Arabi predicted that people will start innovating more on architecture, EDA and circuits.

Banna at GlobaslFoundries was bolder: “With innovation, Moore’s Law can be extended. But traditional Moore’s Law improvements stopped at 130nm.”

Instead, a series of process innovations had kept the industry on the Moore’s Law improvement track. He argued that the latest of these, the shift to finFETs, has delivered a device that is so strong that “I can say why do I need a nine-track library when I can a get similar performance within an 8 or 7.5 track library? It provides a different way of scaling.”

Liebmann offered an economic perspective: “Moore’s Law is a really bad economic law. To offer two times performance every two years is not a sustainable economic platform. We have to ensure that the value of doubling is really recognized. It is time we as an industry take back more of the share of that value proposition.”

Brand at Applied Materials argued that “we have a clear pathway to 7nm or 5nm on how to build transistors, but we still need to scale to get power reduction.

From the process point of view, Arabi at Qualcomm argued that the move to new technology nodes is accelerating: “It’s exponentially more complicated, but we had to accelerate to meet customers’ needs.”


Patterning devices continues to be one of the major challenges at these very deep submicron dimensions. Asked about the current state of lithography, Liebmann at IBM argued that EUV systems “will come to life any day now.

“We’re very optimistic that EUV will play a role in 7nm nodes,” he added. “We are planning to avoid quadruple patterning and move back to EUV,” for this node.

He said that the move to EUV is not entirely an economic argument: the design restrictions to make a self-aligned quad-patterned process work would be great.

“We need to keep wavelength scaling going otherwise design restrictions become intolerable.”

Liebmann: We need to keep wavelength scaling going otherwise design restrictions become intolerable

Image Liebmann: We need to keep wavelength scaling going otherwise design restrictions become intolerable

Banna at GlobalFoundries said that he wanted to use EUV but the throughput is still too low: “Today it is not at the economic point but there’s a lot of innovation that will make it happen.”

Liebmann reiterated his enthusiasm for EUV: “I’m quite optimistic. The tool is installed, the masks have been ordered, we just need someone to turn on the light source and pass some photons.

“This year we will find out if EUV is a reality or whether we will have to use other technologies,” he added. “This will be the decisive year to find out and we are weeks away, if not days away.”

Brand pointed out that if EUV is introduced at 7nm, it will still be necessary to use double-patterning on the critical layers. Liebmann argued that would still be better than pushing for even greater degrees of multiple patterning with 193nm illumination.

“Explain to me how to do first metal with quad patterning,” he said. “It requires design innovation at a very fundamental level. Eventually we will get there but we are trying to put it off, because it will not be well received.”

Asked whether the advent of an economically viable EUV solution would enable design rules to be relaxed again, Arabi argued that every new node brings with it more design rules, process corners, design-rule checks and design for manufacturing issues.

“That’s why we like EUV, because it has the promise of doing away with double patterning and triple patterning,” he said.

Interconnect scaling

Liebmann argued that interconnect scaling offered another challenge.

“At 14nm the wiring pitch is 64nm,” he said. “At 7nm the wiring pitch is 32nm. With 193nm illumination, we can do 40nm pitch, and double patterning will not get you to 32nm, so we will be looking at something else.”

He argued that EUV lithography will enable the industry to make 32nm, 1D gratings, which will demand very restrictive design rules.


What materials will have to be pressed into service to keep the industry moving to denser nodes?

Brand at Applied Materials argued that it is fairly clear that in terms of increasing the electrostatic coupling to, and control of the gate, the industry will have to gate-all-around structures. Beyond the silicon and germanium used in current processes, the industry may have to move to 3:5 materials, but as brand pointed out “lots of things have to be perfected [to use them] ,such as creating the gate dielectrics and doing the doping.”

Liebmann pointed out that as wiring moves to a 32nm pitch, the space for actual wiring material will be under pressure because of issue with scaling the lining materials necessary to stop the metallisation diffusing in to the bulk.

Brand said there were good ideas on the table to scale down the lining materials for a few more nodes.

He brought up another issue that needs addressing: at 32nm, the dimensions of the wiring are approaching that of the mean free path of electrons in copper, which increases their resistivity. This may mean that it will make sense to use tungsten, in which the electron mean free path is shorter than in copper, as the best conductor over short distances.

Arabi at Qualcomm said that there are good ideas for transistor scaling at 7nm and 5nm, such as moving to 3:5 materials, using silicon/germanium, and building nanowires, but “it’s really the interconnect that worries me and the power density.”

Asked about the potential of grapheme, he said that as a designer, he needed both mobility and a band gap. To achieve this would mean doping the grapheme, which might in turn undermine its advantages as a conductor.

The economics

Moore’s Law may continue to scale, in one way or another, for a number of nodes yet. The question is, who will be able to afford to use the resultant processes.

Banna at GlobalFoundries said that a new fab costs $6bn, and so “when you build such a fancy fab you want to ensure customers are asking for high-end products. If I don’t recover the costs, there’s no business.”

Arabi at Qualcomm said that as a fabless company, “going to a new node from the design point of view costs one to two billion dollars, trending towards the higher side of that.”

Brand at Applied Materials said his company spent $1bn on R&D for each new node.

How can this be sustained? Arabi at Qualcomm said that the 28nm node is “the node before the cliff, a technology that is there to stay for a long time,” which will give a lot of opportunity to get the cost out of it.

“From this point forward it will be a segregated market, especially with markets like the Internet of things which could drive huge volumes,” he added.

Banna at GlobalFoundries argued that “the Internet of things can give enough margin to foundries running on depreciated fabs to support advanced node development.”

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors