Python provides the link for speed checks at Sondrel
Design-services company Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the performance analysis of high-level architectures that avoids the need to synthesis the full design to RTL first.
The analysis infrastructure is an evolution of the company’s Performance Verification Environment (PVE), which it has been developing for several years. The environment is used to quickly generate models using a SystemC chassis that allow various parameters can be easily tweaked to see what effect the changes have on performance.
According to the company, each variant can be generated and run in a few hours whereas trying to assess each variant using full RTL simulations would take weeks for each variant, at the cost of some accuracy in the analysis of how transactions may interfere with each other in the final system. Sondrel has used the approach as it is easy to deploy and can help reduce the risk of a design not meeting its specifications.
The methodology starts by using an exploration platform to capture typical transaction traces from the system-level architecture. Those traces are then used to represent use-cases of how the system is likely to perform, acting as stimuli to more detailed bus and interconnect models. The idea is that the simulations run against these traces at RTL or a more detailed functional model will show up potential bottlenecks such as contention and buffer limitations.
Image The two main flows in Sondrel's Python-based PVE
To run the traces against the various interconnect, memory-controller and other SoC-infrastructure IP cores, Sondrel uses a Python-in-SystemC embedding technique built on top of Synopsys’ VCS, DVE and Verdi products though the company says is also capable of supporting tools from other EDA vendors, such as Siemens EDA’s Questa and Cadence Xcelium. Sondrel has used Python for greater flexibility in connecting the SystemC test harness to the various IP cores and to convert transactions between the two domains.
Having run a series of cycle-accurate simulations of the architectural model, system architect typically provide a script to organise captured transaction traces into use-cases that exercise the SystemC/Python/RTL simulation. The outputs generally captured as FSDB waveform databases that allow debugging in tools such as Verdi, DVE, Questa and Xcelium.
Sondrel says the benefits of this approach are that subtle RTL issues become apparent that may not have appeared in the purely SystemC exploration platform. This can be done in advance of preparation of the UVM environment. The company believes architects and performance engineers find it easier to use this approach rather than trying to work with UVM as they are more likely to have experience with Python than SystemVerilog.
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