Onchip sensors aim for finer-granularity heat measurements

By Chris Edwards |  No Comments  |  Posted: June 10, 2020
Topics/Categories: Blog - IP  |  Tags: , , ,  | Organizations:

Moortec has reworked its onchip thermal-sensing architecture for the 5nm node to allow for finer-grained use on SoCs.

According to the company, the Distributed Thermal Sensor (DTS), takes up seven times less area than conventional architectures in situations where a number of sensors need to be spread across the SoC. The aim is to make it possible for SoC designers to place the sensors inside large blocks and processor cores to measure their operating temperature directly.

“We’ve taken the topology of our long-standing thermal sensing solution, all our associated learning, as well as customer inputs, to produce the new architecture for the DTS,” said Ramsay Allen, Moortec marketing manager. “The area savings come about through the small remote sensors being repeated and distributed, which feedback to the central hub.”

According to Moortec CEO Stephen Crosher, the company has opted for an architecture that supports relatively high sampling rates to keep better of instantaneous temperature changes that are commonly encountered in SoCs, such as those aimed at HPC and AI applications, that have to deal with bursts of activity.

“We’ve seen a clear need for tighter thermal control of semiconductor devices. Multi-core architectures applied to AI, automotive, consumer and many other applications, benefit from highly distributed sensing schemes to minimize system-level power consumption, optimize data throughput, and improve product lifetimes,” Crosher said.

The DTS has been designed for TSMC’s N5 process and has been licensed to several lead customers.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors