signal promotion


July 30, 2015

10nm flow reveals complexity of finFET design process

Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors