Cliff Hou, TSMC VP R&D, on the route to 10nm – and beyond

Stronger collaboration in the chip ecosystem and more subtle tradeoffs in design will be necessary to develop and use future technology nodes, according to Cliff Hou, VP of R&D at TSMC.

Speaking at DAC 2014 in San Francisco this week, Hou laid out his vision of the challenges and opportunities that future nodes will bring.

Reviewing progress to date, he said that from a design point of view, the introduction of 28nm brought HKMG and layout-dependent effects, which reduced overall design margin.

At 20/16nm, the requirement to use double patterning lithography means solving the colouring issue, which EDA tools are handling. The quantisation of channel widths in finFET processes means that more care needs to be taken with the design: “If you don’t do the design carefully you could lose one fin out of a set of four, which would mean losing 25% of your performance,” Hou said.

At 10nm, lithography is likely to involve the use of (expensive) multi-patterning techniques to define the critical layers of the design.

Hou added that Moore’s Law had created an expectation that every new process generation is  will halve the chip area, increase the performance by 25 to 30%, and decrease power consumption by 40 to 50%.

“Looking forward to 10, 7 and 5nm from the process point of view, we can still provide power/performance/area advantages but the development costs and design costs will be very high.”

He added that the industry will need all its ecosystem partners to work together in order to extract every per cent of the power, performance and area advantages that are available.

“Every penny will count for 10nm and 7nm processes,” he added.

Hou predicted that semiconductor companies will still be using immersion lithography at 10nm and 7nm to continue geometric scaling, but from the device point of view “the question is can I find a device which will offer 25 to 30% speed increases at the same power?”

Other upcoming challenges include  escalating parasitics in the interconnect, and the need to increase the rate at which new processes ramp to volume, regardless of their increased complexity.

In terms of the ecosystem, Hou said the challenges include finding a way to make the best use of all the power, performance and area that a new process will offer, having enough time to find that solution before customers want to start their designs, and deciding whether Moore’s Law scaling is the only way to improve system performance.

In lithography, Hou said TSMC would push immersion approaches as far as possible, using spacer technology to deliver 40nm metal pitches for 10nm, and double spacer technology to achieve 30nm pitch for 7nm. TSMC is also considering directed self-assembly as an option at 16 nm half pitch.

In devices, Hou said the company will continue to use finFETs for 16 and 10nm, but that at 7nm or 5nm he expected to shift to a nanowire or gate-all-around structure. It may be that at this point the company will introduce 3:5 materials to enable supply voltages of half a volt and below.

In terms of interconnect at 16 and 10nm, the rapidly rising resistivity of the narrow wires caused by tight wire pitches is increasing RC time constants, slowing signals down. It may be the case that some parts of a design will therefore have to use a different metal pitch to relieve this problem.

Production ramp will also be a challenge, with the 28nm process coming to market “much faster” than the previous 40nm node, with the shift to 20nm beginning the same and the shift to 16nm “even faster than 20nm.”

Hou said there will have to be greater design and technology co-optimisation at advanced nodes, arguing that today’s approach to design is to find a local optimum and take that to mean that you have found a global optimum; that using the shortest wire means achieving the best performance; that the best density will give the best scaling; and that the best power/performance/area will naturally have the best cost.

“This ‘divide and conquer’ approach used to work but looking forward, higher-drive cells may not yield the best performance and power because of parasitics. And optimising for layout, then for yield and manufacturing won’t work any more,” sad Hou.

“We need to work in a concurrent way between EDA and process,” he added. “The conventional wisdom that led to our success in the past will no longer working the future.”

The impact of this new reality will be felt in interconnect schemes.

“We have to use the metal pitch in interconnect in a smart way,” said Hou, “for example increasing the metal pitch a little to reduce the resistance a lot, as well as taking routing to the higher metal layers. If you don’t use the metal right you can degrade the performance by 15 to 20%.”

This has a number of implications, such as a need to extract resistance more accurately during design, and introducing block-dependent metal pitch and width so that it is possible to use a wider pitch for high-performance blocks and a tighter pitch for dense blocks.

“It’s a totally different approach from what we do today,” said Hou.

Meeting manufacturing constraints is likely to mean further restrictions on layout styles, and perhaps even the imposition of one-dimensional layout strategies. Hou believes this approach can deliver shorter routing lengths and therefore less capacitance, as well as improved gate density.

In terms of IP, Hou said providers need to consider the trade-offs between local and global optimisations.

“In the past we believed that if I make IP smaller my chip will be smaller,” he said. “But the smaller cell may no longer lead to the smallest logic area because of potential double-patterning and pin-access violations.

“We may end up using much larger areas to compensate for the overly dense blocks. IP providers have to think about how their users will use their solutions.”

At 10nm, designers will also be challenge by the ends to colour their designs, that is to define which of a number of masks used to pattern each critical layer should carry each of the polygons on that layer. This is being handled by EDA tools at 16nm.

“This requires a new design flow methodology,” said Hou. “Every step of the flow has to be coloured or the whole thing breaks: your IP has to be colour-compliant, the floorplan has to be colour-compliant, and so does the placement and the routing.”

In terms of technology complexity, Hou said it will increase as follows between the 28nm and 10nm nodes:

• DRC deck sizeable increases 2.4x
• Place and route key features increases 6.3x
• RC key features increase 3.9x
• STA/SI/PI key features increase 2.3x

“The challenge is there,” said Hou. “With all those challenges, will customers slow down their designs? No.”

He argued that challenges mean opportunities that need to be met with a new ecosystem partnership.

“With a design partner you have to define the device, the power/performance/area options, the design rule options and the test vehicle plan,” he said.

“With an EDA partner you have to work on design solution exploration, define the design solutions and then work on tool enhancements. If any part is missing it will cause the whole collaboration model to break.”

To progress beyond 10nm, the next step may mean a shift to relying on packaging technology to deliver power/performance/area benefits. Hou cited technology options such as FCPoP, InFOPoP, 3D TSV, and 2.5D CoWoS.

“There are three questions with this: is the technology ready, is it cost competitive and how do I use it,” said Hou. “3D IC technology is ready or almost ready and the cost will become very competitive pretty soon.”

He added that the fact that scaling to 10nm and 7nm is so challenging and costly creates opportunities for TSMC, with wafer-level integration paving the way for future systems beyond SoC.