Kioxia looks to waferscale flash drives for fast, low-cost storage
Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.
Author Archives: Chris Edwards
Transistor stacks piled high at VLSI
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Onchip sensors aim for finer-granularity heat measurements
Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.
Real Intent tries to shift left on DFT
Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
IEDM plans for San Francisco in December
The IEEE plans to stage the 66th International Electron Device Meeting as a physical event in mid-December.
DVCon 2020 to repeat sessions online
DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Nanometer scaling puts focus on power at VLSI in June
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
The price of reliability is constant vigilance
Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
Ultrawide neural engine fills a hole
Centaur opted for a superwide SIMD engine in an accelerator for a multicore x86 aimed at edge server applications that could take full advantage of spare die area.
Scaling drives targeted analysis of reliability issues
Keynotes at this year’s IRPS conference focused on the way in which scaling is forcing changes to the way that the reliability aspects of semiconductors are examined.