Scaling drives targeted analysis of reliability issues
Keynotes at this year’s IRPS conference focused on the way in which scaling is forcing changes to the way that the reliability aspects of semiconductors are examined.
Author Archives: Chris Edwards
Arm extends free access to core designs for startups
Arm has put together a program based on its existing Flexible Access model that is intended to provide early-state startups with a broader list of cores they can prototype before needing to take out a full licence.
IP partnership aims to crack down on physical hacks
UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
Feed fake news to hardware hackers
Intel describes active countermeasures for physical attacks at CICC as part of a trend towards more adaptive IoT silicon.
CEVA splits vectors for more efficient 5G
CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
Wind River sets up labs site to drive IoT and AI applications
Wind River has set up a site to distribute more experimental libraries based around its real-time operating systems and provide a hub for users to interact.
Accellera moves to working-group stage for functional-safety standard
Accellera has set up a working group with the aim of developing interoperability standards for functional safety.
Debug connects with manufacturing test to cut product recall costs
UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
Arm adds AI to Cortex-M cores
Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
SureCore provides 30-day test for SRAM compiler
SureCore has started running 30-day trials of its low-power memory compiler.