A keynote delivered by Shigeo Ohshima, Kioxia’s technology executive for solid-state drive applications engineering, at the VLSI Symposia illustrated the way in which choices for integration have expanded as classical 2D scaling peters out.
Ohshima touted the possibility of solid-state flash drives (SSDs) that could undercut the pricing of rotating hard disk drives by taking advantage of waferscale integration. He said a key problem overall remains “how to realize high bit density while keeping the cost as low as possible” when techniques such as multilayer memories increase cost with each successive layer. “We should consider the combination of x-y shrink and layer stacking,” he said.
Although much of the focus in NAND flash memory has been the used of 3D structures that make it possible to build strings of flash cells more than a hundred bits tall, Ohshima noted there are potential 2D scaling opportunities, such as continuing to reduce the size of the hole that is etched to make the string in the first place. He described a number of layout changes that might provide incremental changes to string density.
Moving to the waferscale provides a disruptive opportunity when assessing cost at the system level and moving to “flash native solution”, he argued. “By skipping the regular flash memory and SSD manufacturing processes such as assembling, packaging, and drive building, there will be a huge possibility to drastically reduce the cost and lead time for manufacturing.”
The ”wafer-level SSD” proposed by Ohshima would employ direct probes to each of the individual chips on an undiced wafer. “They can be probed and operated simultaneously. It would enable the parallel operation of hundreds of chips on a single wafer,” he claimed.
Although the cost could be as low as 20 per cent of that of conventional flash-based drives, and offer a price-per-bit similar to that of hard-disk drives, the wafer-level SSD would not be aimed at entry-level servers. Instead, they would take advantage of the parallel operation to accelerator big-data applications. Ohshima used the example of expansion microscopy, a novel technique that involves the capture of numerous images quickly, to illustrate where the wafer-level SSD might fit.
Ohshima said the wafer-level SSD is at the R&D stage as there will be challenges in developing cost-effective waferscale probing techniques. But in the near term, he pointed to other opportunities to parallelize flash I/O. One is the virtual multi logical unit number (VML) controller, which provides simultaneous access to the physical planes in each flash chip. “Each plane operates almost independently and is able to define its own timing and addressing,” he explained, which should translate into much better random-access performance compared to the serialized approach used today.
Although Kioxia expects to continue to support PCIe-based interfaces and take advantage of the migration to Gen4 to improve bandwidth, the company is also looking to integrate direct Ethernet support into the flash controllers. This would make it easier to build shared storage arrays that connect directly to the data-center network. The integration would help reduce the bill-of-materials needed for those network arrays, he said, providing another system-level approach to cost.