Flow stability and chip reliability top the papers at DVCon Europe
The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.
aging
The price of reliability is constant vigilance
Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
Cadence opens three fronts on mixed-signal failures
Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.