Author Archives: Chris Edwards

About Chris Edwards

Chris Edwards has spent a long time covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology. His work has appeared in a variety of international newspapers including The Guardian, The Daily Telegraph, The Age and the South China Morning Post.
October 7, 2020

Arm seeks to define baseline software compatibility for IoT and edge devices

SystemReady program takes server firmware and operating system compatibility concepts into the embedded and IoT space.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
September 14, 2020

Aprisa team to be doubled after Mentor purchase

Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
September 14, 2020

nVidia commits to buy Arm from Softbank

Graphics and AI specialist nVidia has been confirmed as the buyer of Arm from Softbank Vision Fund in a transaction worth up to $40bn, with the fund retaining a 10 per cent share in Arm if the deal completes.
Article  |  Topics: HPC, Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: ,
August 17, 2020

Cadence uses machine learning to trim constrained-random runtimes

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 31, 2020

Open-RAN puts more focus on emulation in testing programs

Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , , , ,   |  Organizations:
July 27, 2020

Open and proprietary verification tools home in on RISC-V core quality

DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
July 23, 2020

Accellera IP security group expects standard by year end

The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
July 21, 2020

DAC Pavilion focuses on cloud-scaling issues

Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.
July 21, 2020

3D integration technologies will blend says TSMC chief scientist

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,