April 15, 2024
The flat nature of traditional IC packaging design struggles to cope with the chiplet era. Homogeneous disaggregation offers an alternative.
April 15, 2024
The technique is becoming increasingly important for designs that need to be flexible, compact and lightweight.
April 11, 2024
DTCO (design technology co-optimization) looks to address systemic verification challenges but the process still needs to be extended.
April 11, 2024
Make it easier to capture issues in 2.5D and 3D designs with multiple chiplets and emerging challenges with this 'shift left' approach.
March 29, 2024
How the various features within today's Calibre physical verification family help designers shift left tasks and cut time-to-market.
March 18, 2024
Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.
March 14, 2024
Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.
February 22, 2024
Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
February 1, 2024
Cadence has introduced a platform for performing thermal and thermal-stress analysis of subsystems, from 2.5D and 3DICs to PCBs and complete electronic assemblies.
January 21, 2024
A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.